The Xgig 5P16, our flagship system, supports full-featured Analyzer, Exerciser and Jammer functionality on the same chassis. The Xgig 5P16 Chassis also Supports Analyzer, Exerciser and Jammer Functions As shown in the graphic below, a VIAVI Xgig 5P8 can be bifurcated into two links of 4-lanes each-and a 5P16 can be bifurcated into two links of 8-lanes each or four links of 4-lanes each. The graphic below is an example of a 16-lane Analyzer bifurcated into four independent links for separate simultaneous tests by multiple users.īifurcation works by dividing a port that is normally one link into two or more links. They can log in remotely, from anywhere in the world, if they have access to a network. Users don’t have to be in the same physical location as the Analyzer either. Now, multiple users can log into one VIAVI Xgig® 5P16 or 5P8 Analyzer at the same time to perform simultaneous independent tests.īifurcation Enables Simultaneous Multi-User (SMU) Flexibility Traditionally, PCI Express® protocol analysis is performed with one user conducting a single test on dedicated, single function equipment. Medusa Labs Test Tools Suite (MLTT) is an application-based data and signal integrity testing tool enabling developers to identify, locate and resolve errors through stress testing. Xgig Trace Control is the system settings user interface the operator uses to configure the system for testing.It enhances contextual debugging and provides smart analytics for serial protocols Xgig Serialytics™ builds on Xgig Expert to expose hidden behaviors and events in a trace.Xgig Expert™ is a user-friendly interface that aids in rapid data interpretation, performance analysis and troubleshooting.The Xgig PCIe 5.0 platform is supported by the Xgig Tool Suite including: VIAVI offers a full range of popular PCIe Interposers including: Interposers enable capture of communication between a host system and a device under test (DUT). Essential for mission-critical products.Helps ensure devices perform exactly the way they need to in real world environments.Simulation of network traffic in real time creates an important litmus test for PCIe 5.0 hardware.Best for system tests and error recovery analysis.Jammers operate in-line between the CPU and endpoints and inject errors in the communication between actual system devices. PCIe 4.0 is the highest level of compliance certification currently performed by the PCI-SIG. The Xgig Exerciser is approved by the Peripheral Component Interconnect Special Interest Group (PCI-SIG) for use in PCI Express (PCIe) 4.0 protocol compliance certification testing performed at PCI-SIG compliance workshops. Host or Root Complex mode (left) is used to test endpoints.Įndpoint mode (right) is used to test host systems, switch ports and CPUs. Ideal for component level analysis and debuggingĮxercisers have two modes of operation.Replaces the communication link partner and provides full control over Root Complex or Endpoint testing as shown in the diagram.Valuable tool for debugging difficult protocol communication problems because it provides full, bit-level, repeatable control over the PCIe data traffic.The VIAVI Solutions Xgig® Exerciser for PCIe 5.0 brings turn-key compliance test capability to the Xgig PCIe product portfolio. Superior memory, storage capacity, and segmentation for higher volume upstream and downstream traffic capture allows long sequences to be recorded with specific packets filtered out for robust protocol analysis. It is the industry standard for solid state drives (SSDs) in all form factors (U.2, M.2, AIC, EDSFF).įully downward compatible protocol analyzers capable of supporting 32GT/sec data link speed operations, such as the VIAVI Xgig Analyzer, are invaluable for PCIe 5.0 testing and debugging. NVM Express® (NVMe®) defines how host software communicates with non-volatile memory across multiple transports like PCI Express® (PCIe®), RDMA, TCP and more.Compute Express Link (CXL) is an industry-supported Cache-Coherent Interconnect for Processors, Memory Expansion and Accelerators.For example, revised Electrical Idle Exit Ordered Set (EIEOS) and clocking features have impacted test practices at both the hardware and system levels.Īlternate protocols also require full test support, as this improved versatility now permits other protocols to leverage the proven PCIe physical layer stack. With the significant increase in data rates, test standards and practices continue to be challenged with each new PCIe release, and PCIe gen-5 is no exception.
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